1. Field of the Invention
The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a vertically stacked semiconductor package with improved physical strength and a method of manufacturing the same.
2. Description of the Related Art
As semiconductor devices are used in a wider range of application fields, the importance of semiconductor packages that protect semiconductor chips from mechanical damage and extend their functions to the outside has significantly increased. Semiconductor packages come in various shapes and with various characteristics.
Stack semiconductor packages are designed so that two semiconductor packages are vertically stacked on each other and combined together, thus increasing the memory capacity by a factor of two or more. With this increased capacity, the semiconductor packages can be used in the growing market of large-capacity servers and network applications.
FIG. 1 is a cross-sectional view of a conventional stack semiconductor package 10. Referring to FIG. 1, the conventional stack semiconductor package 10 includes first and second semiconductor packages 20 and 40 that are electrically connected to each other by a conductive adhesive or solder 34 and operates as a single semiconductor package. A method of manufacturing the first semiconductor package 20 involves mounting a first semiconductor chip 26 on a first die pad 22, connecting the first semiconductor chip 26 with inner leads 24 by first wires 28, and molding the first semiconductor package using first sealing resin 30. A method of manufacturing the second semiconductor package 40 includes mounting a second semiconductor chip 46 on a second die pad 42, connecting the second semiconductor chip 46 with inner leads 44 by second wires 48, and molding the second semiconductor package using second sealing resin 50.
However, the conventional stack semiconductor package is susceptible to breakage due to stress concentration at a connecting portion A between the first and second semiconductor packages 20 and 40 in response to changes in the external environment and conditions. This can be easily verified by using a temporal cycle test, which is a reliability test used to examine the physical status of a semiconductor package when being alternately subjected to extremely low and high temperatures.